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8-/10-/12-bit high bandwidth multiplying dacs with serial interface ad5426/ad5432/ad5443 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2009 analog devices, inc. all rights reserved. features 3 v to 5.5 v supply operation 50 mhz serial interface 10 mhz multiplying bandwidth 2.5 msps update rate inl of 1 lsb for 12-bit dac 10 v reference input low glitch energy < 2 nv-s extended temperature range ?40c to +125c 10-lead msop package pin-compatible 8-, 10-, and 12-bit current output dacs guaranteed monotonic 4-quadrant multiplication power-on reset with brownout detection daisy-chain mode readback function 0.4 a typical power consumption applications portable battery-powered applications waveform generators analog processing instrumentation programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5426/ad5432/ad5443 1 are cmos 8-, 10-, and 12-bit current output digital-to-analog converters (dacs), respectively. these devices operate from a 3 v to 5.5 v power supply, making them suitable for battery-powered applications and many other applications. these dacs use a double buffered, 3-wire serial interface that is compatible with spi ? , qspi ? , microwire ? , and most dsp interface standards. in addition, a serial data out pin (sdo) allows for daisy-chaining when multiple packages are used. data readback allows the user to read the contents of the dac register via the sdo pin. on power-up, the internal shift register and latches are filled with 0s and the dac outputs are at zero scale. as a result of manufacturing on a cmos submicron process, the parts offer excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 mhz. the applied external reference input voltage, v ref , determines the full-scale output current. an integrated feedback resistor, r fb , provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. the ad5426/ad5432/ad5443 dacs are available in small, 10-lead msop packages. 1 u.s. patent no. 5,689,257 functional block diagram sclk sync ad5426/ ad5432/ ad5443 v ref i out 2 i out 1 r fb r 8-/10-/12-bit r-2r dac dac register sdin v dd gnd power-on reset control logic and input shift register input latch sdo 03162-001 figure 1.
ad5426/ad5432/ad5443 rev. c | page 2 of 28 table of contents specifications ..................................................................................... 3 ? timing characteristics ..................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? te r m i no l o g y .................................................................................... 14 ? theory of operation ...................................................................... 15 ? circuit operation ....................................................................... 15 ? single-supply applications ....................................................... 17 ? positive output voltage ............................................................. 17 ? adding gain ................................................................................ 18 ? dacs used as a divider or programmable gain element ... 18 ? reference selection .................................................................... 18 ? amplifier selection .................................................................... 18 ? serial interface ............................................................................ 20 ? microprocessor interface .......................................................... 21 ? pcb layout and power supply decoupling ................................ 23 ? evaluation board for the ad5426/ad5432/ad5443 series of dacs ............................................................................................ 23 ? operating the evaluation board .............................................. 23 ? overview of ad54xx and ad55xx devices ............................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 2/09rev. b to rev. c changes to low power serial interface section and daisy- chain mode section ....................................................................... 20 updated outline dimensions ....................................................... 28 11/08rev. a to rev. b changes to ordering guide .......................................................... 28 5/05rev. 0 to rev. a updated format .............................................................. universal changes to specifications ............................................................ 3 changes to figure 42 .................................................................. 16 change to figure 45 ................................................................... 17 change to figure 46 ................................................................... 18 changes to table 7, table 8, and table 9 ................................. 19 additions to microprocessor interface section ...................... 21 2/04revision 0: initial version
ad5426/ad5432/ad5443 rev. c | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v; temperature range for y version: ?40c to +125c; all specifications t min to t max , unless otherwise noted; dc performance measured with op177; ac performance with ad8038, unless otherwise noted. table 1 . parameter min typ max unit conditions static performance ad5426 resolution 8 bits relative accuracy 0.25 lsb differential nonlinearity 0.5 lsb guaranteed monotonic ad5432 resolution 10 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5443 resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 10 mv gain error temperature coefficient 1 5 ppm fsr/c output leakage current 10 na data = 0x0000, t a = 25c, i out 1 20 na data = 0x0000, t = ?40c to 125c, i out 1 reference input 1 reference input range 10 v v ref input resistance 8 10 12 k input resistance tc = ?50 ppm/c r fb resistance 8 10 12 k input resistance tc = ?50 ppm/c input capacitance code zero scale 3 6 pf code full scale 5 8 pf digital input/output 1 input high voltage, v ih 1.7 v input low voltage, v il 0.6 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance 1 reference multiplying bandwidth 10 mhz v ref = 3.5 v; dac loaded all 1s output voltage settling time v ref = 10 v; r load = 100 , dac latch alternately loaded with 0s and 1s measured to 16 mv of fs 50 100 ns measured to 4 mv of fs 55 110 ns measured to 1 mv of fs 90 160 ns digital delay 40 75 ns interface delay time 10% to 90% rise/fall time 15 30 ns rise and fall time, v ref = 10 v, r load = 100 digital-to-analog glitch impulse 2 nv -s 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error dac latch loaded with all 0s, v ref = 3.5 70 db 1 mhz 48 db 10 mhz
ad5426/ad5432/ad5443 rev. c | page 4 of 28 parameter min typ max unit conditions output capacitance i out 1 12 17 pf all 0s loaded 10 12 pf all 1s loaded i out 2 22 25 pf all 0s loaded 10 12 pf all 1s loaded digital feedthrough 0.1 nv-s feedthrough to dac output with sync high and alternate loading of all 0s and all 1s analog thd 81 db v ref = 3.5 v p-p, all 1s loaded, f = 1 khz digital thd clock = 1 mhz, v ref = 3.5 v, c comp = 1.8 pf 50 khz f out 73 db 20 khz f out 74 db output noise spectral density 25 nv/hz @ 1 khz sfdr performance (wide band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 75 db 20 khz f out 76 db sfdr performance (narrow band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 87 db 20 khz f out 87 db intermodulation distortion 78 db clock = 1 mhz, f 1 = 20 khz, f 2 = 25 khz, v ref = 3.5 v power requirements power supply range 3.0 5.5 v i dd 0.6 a t a = 25c, logic inputs = 0 v or v dd 0.4 5 a t = ?40c to +125c , logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization, not subject to production testing.
ad5426/ad5432/ad5443 rev. c | page 5 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v; temperature range for y version: ?40c to +125c; all specifications t min to t max , unless otherwise noted. table 2. parameter 2.5 v to 5.5 v 4.5 v to 5.5 v unit conditions/comments f sclk 50 50 mhz max max clock frequency t 1 20 20 ns min sclk cycle time t 2 8 8 ns min sclk high time t 3 8 8 ns min sclk low time t 4 1 13 13 ns min sync falling edge to sclk active edge setup time t 5 5 5 ns min data setup time t 6 3 3 ns min data hold time t 7 5 5 ns min sync rising edge to sclk active edge t 8 30 30 ns min minimum sync high time t 9 2 80 45 ns typ sclk active edge to sdo valid 120 65 ns max 1 falling or rising edge as determined by control bits of serial word. 2 daisy-chain and readback modes cannot oper ate at maximum clock frequency. sdo timing sp ecifications measured with load circuit , as shown in figure 4. db15 db0 sclk sync din alternatively, data may be clocked into input shift register on rising edge of sclk as determined by control bits. timing as per above, with sclk inverted. t 1 t 8 t 4 t 3 t 2 t 5 t 6 t 7 03162-002 figure 2. standalone mode timing diagram db15 (n) db0 (n) db15 (n + 1) db0 (n + 1) sclk sdin sdo alternatively, data may be clocked into input shift register on rising edge of sclk as determined by control bits. in this case, data would be clocked out of sdo on falling edge of sclk. timing as per above, with sclk inverted. t6 db15(n) db0(n) t 1 t 2 t 5 t 9 t 6 t 4 t 3 t 7 t 8 sync 03162-003 figure 3. daisy-chain and readback modes timing diagram
ad5426/ad5432/ad5443 rev. c | page 6 of 28 absolute maximum ratings transient currents of up to 100 ma do not cause scr latch-up. t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i out 1, i out 2 to gnd ?0.3 v to v dd + 0.3 v logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating temperature range extended industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 10-lead msop ja thermal impedance 206c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at sclk, sync , and din are clamped by internal diodes. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 200 ai ol 200 ai oh to output pin c l 20pf v oh (min) + v ol (max) 2 03162-004 figure 4. load circuit for sdo timing specifications esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without de tection. although th is product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5426/ad5432/ad5443 rev. c | page 7 of 28 pin configuration and fu nction descriptions i out 1 1 i out 2 2 gnd 3 sclk 4 sdin 5 r fb 10 v ref 9 v dd 8 sdo 7 sync 6 ad5426/ ad5432/ ad5443 top view (not to scale) 03162-005 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 i out 1 dac current output. 2 i out 2 dac analog ground. this pin sh ould normally be tied to the analog ground of the system. 3 gnd digital ground pin. 4 sclk serial clock input. by default, data is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of sclk. the device can accommodate clock rates up to 50 mhz. 5 sdin serial data input. data is clocked in to the 16-bit input register on the acti ve edge of the serial clock input. by default, on power-up, data is clocked in to the shift register on the falling edge of sclk. the control bits allow the user to change the active edge to rising edge. 6 sync active low control input. this is the frame sy nchronization signal fo r the input data. when sync goes low, it powers on the sclk and din buffers, and the input shift register is enabled. da ta is loaded to the mode, the serial interface counts clocks, and data is latched to the shift register on the 16th active clock edge. 7 sdo serial data output. this allows a number of parts to be daisy-chained. by de fault, data is cloc ked into the shift register on the falling edge and out via sdo on the risi ng edge of sclk. data is always clocked out on the alternate edge to loading data to the shift register. writing the readback cont rol word to the shift register makes the dac register contents available for readback on the sdo pin, clocked out on the opposite edges to the active clock edge. 8 v dd positive power supply input. these parts can be operated from a supply of 3 v to 5.5 v. 9 v ref dac reference voltage input. 10 r fb dac feedback resistor pin. establ ish voltage output for the dac by connecting to external amplifier output.
ad5426/ad5432/ad5443 rev. c | page 8 of 28 typical performance characteristics 03162-006 code 250 0 50 100 150 200 inl (lsb) 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 t a = 25c v ref = 10v v dd = 5v 03162-009 code 250 0 50 100 150 200 inl (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.15 ?0.20 t a = 25c v ref = 10v v dd = 5v figure 6. inl vs. code (8-bit dac) figure 9. dnl vs. code (8-bit dac) 03162-007 code 0 200 400 600 800 10000 inl (lsb) 0.5 0.4 0.3 0.1 0.2 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 t a = 25c v ref = 10v v dd = 5v 03162-010 code 1000 0 200 400 600 800 dnl (lsb) 0.5 0.3 0.2 0.4 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 t a = 25c v ref = 10v v dd = 5v figure 7. inl vs. code (10-bit dac) figure 10. dnl vs. code (10-bit dac) 03162-008 code 4000 0 500 1000 1500 2000 2500 3000 3500 inl (lsb) 1.0 0.6 0.8 0.4 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 t a = 25c v ref = 10v v dd = 5v 03162-011 code 4000 0 500 1000 1500 2000 2500 3000 3500 dnl (lsb) 1.0 0.6 0.4 0.8 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 t a = 25c v ref = 10v v dd = 5v figure 8. inl vs. code (12-bit dac) figure 11. dnl vs. code (12-bit dac)
ad5426/ad5432/ad5443 rev. c | page 9 of 28 03162-012 reference voltage 10 23456789 inl (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 max inl min inl t a = 25c v dd = 5v ad5443 figure 12. inl vs. reference voltage 03162-013 reference voltage 10 23456789 dnl (lsb) ?0.40 ?0.45 ?0.55 ?0.50 ?0.60 ?0.65 ?0.70 min dnl t a = 25c v dd = 5v ad5443 figure 13. dnl vs. reference voltage 03162-014 temperature (c) 140 ?60 ?40 ?20 0 20 40 60 80 100 120 error (mv) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 v dd = 5v v dd = 3v v ref = 10v figure 14. gain error vs. temperature 03162-015 v bias (v) 1.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 lsb 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 t a = 25c v ref = 0v v dd = 3v ad5443 max inl min inl max dnl min dnl figure 15. linearity vs. v bias voltage applied to i out 2 03162-016 v bias (v) 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 lsb 4 2 1 3 0 ?1 ?2 ?3 ?4 ?5 t a = 25c v ref = 2.5v v dd = 3v ad5443 max inl min inl max dnl min dnl figure 16. linearity vs. v bias voltage applied to i out 2 03162-017 v bias (v) 1.5 0.5 0.6 0.7 0.8 1.0 1.1 0.9 1.2 1.3 1.4 voltage (mv) 0.5 0.3 0.4 0.1 0.2 ?0.1 ?0.2 0 ?0.3 ?0.4 ?0.5 offset error gain error t a = 25c v ref = 0v v dd = 3v and 5v figure 17. gain and offset errors vs. v bias voltage applied to i out 2
ad5426/ad5432/ad5443 rev. c | page 10 of 28 03162-018 v bias (v) 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 voltage (mv) 0.5 0.3 0.2 0.4 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 t a = 25c v ref = 2.5v v dd = 3v and 5v gain error offset error figure 18. gain and offset errors vs. v bias voltage applied to i out 2 03162-019 v bias (v) 2.5 0.5 1.0 1.5 2.0 lsb 3 2 1 0 ?1 ?2 ?3 t a = 25c v ref = 0v v dd = 5v ad5443 max inl min inl max dnl min dnl figure 19. linearity vs. v bias voltage applied to i out 2 03162-020 v bias (v) 2.0 0.5 1.0 1.5 lsb 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 t a = 25c v ref = 2.5v v dd = 5v ad5443 max inl min inl max dnl min dnl figure 20. linearity vs. v bias voltage applied to i out 2 03162-021 input voltage (v) 5 01234 current (ma) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v dd = 3v v dd = 5v t a = 25c figure 21. supply current vs. logic input voltage, sync (sclk), data = 0 03162-022 temperature (c) 120 ?40 ?20 0 20 40 60 80 100 i out leakage (na) 1.6 1.2 1.4 0.8 1.0 0.4 0.2 0.6 0 i out 1 v dd 5v i out 1 v dd 3v figure 22. i out 1 leakage current vs. temperature 03162-023 temperature (c) 140 ?60 ?40 ?20 0 20 40 60 80 100 120 current ( a) 0.50 0.40 0.35 0.45 0.30 0.25 0.20 0.15 0.10 0.05 0 v dd = 5v v dd = 3v all 0s all 1s all 0s all 1s figure 23. supply current vs. temperature
ad5426/ad5432/ad5443 rev. c | page 11 of 28 03162-024 frequency (hz) 100m 1 100 1k 10 10k 100k 1m 10m i dd (ma) 3.5 3.0 2.0 2.5 1.5 1 0.5 0 t a = 25c ad5443 loading 010101010101 v cc = 5v v cc = 3v figure 24. supply current vs. update rate 03162-025 frequency (hz) 100m 1 10 100 1k 10k 100k 1m 10m gain (db) 6 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 ?66 ?72 ?78 ?84 ?90 ?96 ?102 loading zs to fs all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier figure 25. reference multiplying bandwidth vs. frequency and code 03162-026 frequency (hz) 100m 1 10 100 1k 10k 100k 1m 10m gain (db) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier figure 26. reference multiplying bandwidthall 1s loaded 03162-027 frequency (hz) 100m 10k 100k 1m 10m gain (db) 3 0 ?3 ?6 ?9 t a = 25c v dd = 5v ad8038 amplifier v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf v ref = 2v, ad8038 c c 1.47pf figure 27. reference multiplying bandwidth vs. frequency and compensation capacitor 03162-028 time (ns) 300 0 50 100 150 200 250 output voltage (v) 0.060 0.030 0.040 0.050 0.010 0.020 ?0.010 0 ?0.020 t a = 25c v ref = 0v ad8038 amplifier c comp = 1.8pf ad5443 v dd 3v, 0v ref nrg = 0.088nvs 0x800 to 0x7ff v dd 5v, 0v ref nrg = 0.119nvs, 0x800 to 0x7ff v dd 3v, 0v ref nrg = 1.877nvs 0x7ff to 0x800 v dd 5v, 0v ref nrg = 2.049nvs 0x7ff to 0x800 figure 28. midscale transition v ref = 0 v 03162-029 time (ns) 300 0 50 100 150 200 250 output voltage (v) ?1.70 ?1.71 ?1.72 ?1.73 ?1.74 ?1.75 ?1.76 t a = 25c v ref = 3.5v ad8038 amplifier c comp = 1.8pf ad5443 v dd 3v, 3.5v ref nrg = 0.647nvs 0x800 to 0x7ff v dd 5v, 3.5v ref, nrg = 0.364nvs, 0x800 to 0x7ff v dd 3v, 3.5v ref nrg = 1.433nvs 0x7ff to 0x800 v dd 5v, 3.5v ref nrg = 1.184nvs 0x7ff to 0x800 figure 29. midscale transition v ref = 3.5 v
ad5426/ad5432/ad5443 rev. c | page 12 of 28 03162-030 frequency (hz) 10m 1 10 100 1k 10k 100k 1m psrr (db) 20 ?20 0 ?60 ?40 ?100 ?80 ?120 t a = 25c v dd = 3v amplifier = ad8038 full scale zero scale figure 30. power supply rejection vs. frequency 03162-031 frequency (hz) 1m 1 10 100 1k 10k 100k thd + n (db) ?60 ?75 ?70 ?65 ?80 ?85 ?90 t a = 25c v dd = 3v v ref = 3.5v p-p figure 31. thd and noise vs. frequency 03162-033 voltage (v) 5.5 2.5 3.0 3.5 4.0 4.5 5.0 threshold voltage (v) 1.8 1.4 1.6 1.0 1.2 0.4 0.6 0.8 0.2 0 t a = 25c v il v ih figure 32. threshold voltages vs. supply voltage 03162-034 f out (khz) 50 01 02 0 4 0 30 sfdr (db) 100 80 60 40 20 0 t a = 25c v ref = 3.5v ad8038 amp ad5443 mclk = 500khz mclk = 200khz m clk = 1m hz figure 33. wideband sfdr vs. f out frequency (ad5443) 03162-035 f out (khz) 50 0 10203040 sfdr (db) 80 60 40 20 0 t a = 25c v ref = 3.5v ad8038 amp ad5426 m clk = 1m hz mclk = 200khz mclk = 500khz figure 34. wideband sfdr vs. f out frequency (ad5426) 03162-036 frequency (hz) 500 0 50 100 150 200 250 300 350 400 450 sfdr (db) 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?90 ?70 ?100 t a = 25c v ref = 3.5v ad8038 amplifier ad5443 figure 35. wideband sfdr f out = 50 khz, update = 1 mhz
ad5426/ad5432/ad5443 rev. c | page 13 of 28 03162-037 frequency (hz) 500 0 50 100 150 200 250 300 350 400 450 sfdr (db) 0 ?20 ?30 ?10 ?40 ?50 ?60 ?70 ?80 ?90 ?100 t a = 25c v ref = 3.5v ad8038 amplifier ad5443 03162-039 frequency (hz) 30 10 14 16 18 12 20 22 24 26 28 sfdr (db) 0 ?20 ?30 ?10 ?40 ?50 ?60 ?70 ?80 ?90 ?100 t a = 25c v ref = 3.5v ad8038 amplifier ad5443 figure 36. wideband sfdr f out = 20 khz, update = 1 mhz figure 38. narrowband (50%) sfdr f out = 20 khz, update = 1 mhz 03162-038 frequency (hz) 75 25 30 35 40 50 55 45 60 65 70 sfdr (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 t a = 25c v ref = 3.5v ad8038 amplifier ad5443 03162-040 frequency (hz) 35 10 15 25 20 30 db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 t a = 25c v ref = 3.5v ad8038 amplifier ad5443 figure 37. narrowband (50%) sfdr f out = 50 khz, update = 1 mhz figure 39. narrowband (50%) imd f out = 20 khz, 25 khz, update = 1 mhz
ad5426/ad5432/ad5443 rev. c | page 14 of 28 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for 0 and full scale and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error gain error or full-scale error is a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref ? 1 lsb. gain error of the dacs is adjustable to 0 with external resistance. output leakage current output leakage current is current that flows in the dac ladder switches when these are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows in the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for these devices, it is specified with a 100 resistor to ground. the settling time specification includes the digital delay from sync rising edge to the full-scale output charge. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-s or nv-s depending upon whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled to show up as noise on the i out pins and subsequently into the following circuitry. this noise is digital feedthrough. multiplying feedthrough error this is the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal, when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower order harmonics are included, such as second to fifth. ( ) 1 2 5 2 4 2 3 2 2 log20 v vvvv thd +++ = digital intermodulation distortion second-order intermodulation distortion (imd) measurements are the relative magnitude of the fa and fb tones generated digitally by the dac and the second-order products at 2fa ? fb and 2fb ? fa. spurious-free dynamic range (sfdr) sfdr is the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. it is the mea- sure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full nyquist bandwidth (half the dac sampling rate, or f s /2). narrow band sfdr is a measure of sfdr over an arbitrary window size, in this case 50% of the fundamental. digital sfdr is a measure of the usable dynamic range of the dac when the signal is a digitally generated sine wave.
ad5426/ad5432/ad5443 rev. c | page 15 of 28 theory of operation the ad5426, ad5432, and ad5443 are 8-, 10-, and 12-bit current output dacs consisting of a standard inverting r-2r ladder configuration. a simplified diagram for the 8-bit ad5426 is shown in figure 40 . the matching feedback resistor, r fb , has a value of r. the value of r is typically 10 k (minimum 8 k and maximum 12 k). if i out 1 and i out 2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref is always constant and nominally of value r. the dac output (i out ) is code-dependent, producing various resistances and capacitances. external amplifier choice should take into account the variation in impedance generated by the dac on the amplifiers inverting input node. v ref i out 2 dac data latches and drivers i out 1 r fb a 2r s1 2r s2 2r s3 2r 2r s8 r r rr 03162-041 figure 40. simplified ladder access is provided to the v ref , r fb , i out 1, and i out 2 terminals of the dac, making the device extremely versatile and allowing it to be configured in several different operating modes. for example, it can be configured to provide a unipolar output, 4-quadrant multiplication in bipolar or single-supply modes of operation. note that a matching switch is used in series with the internal r fb feedback resistor. if users attempt to measure r fb , power must be applied to v dd to achieve continuity. circuit operation unipolar mode using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 41 . when an output amplifier is connected in unipolar mode, the output voltage is given by n ref out d vv 2 ?= where d is the fractional representation of the digital word loaded to the dac, and n is the number of bits. d = 0 to 255 (8-bit ad5426) = 0 to 1023 (10-bit ad5432) = 0 to 4095 (12-bit ad5443) note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. these dacs are designed to operate with either negative or positive reference voltages. the v dd power pin is used by only the internal digital logic to drive the dac switches on and off states. these dacs are also designed to accommodate ac reference input signals in the range of ?10 v to +10 v. with a fixed 10 v reference, the circuit shown in figure 41 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and expected output voltage for unipolar operation (ad5426, 8-bit device). table 5. unipolar code table digital input analog output (v) 1111 1111 ?v ref (255/256) 1000 0000 ?v ref (128/256) = ?v ref /2 0000 0001 ?v ref (1/256) 0000 0000 ?v ref (0/256) = 0 v out = 0 to ?v ref sclk sdin gnd v ref sync i out 2 i out 1 r fb agnd ad5426/ ad5432/ ad5443 r1 r2 a1 v ref v dd v dd c1 notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. microcontroller 03162-042 a1 figure 41. unipolar operation
ad5426/ad5432/ad5443 rev. c | page 16 of 28 bipolar operation in some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. this can easily be accomplished by using another external amplifier and some external resistors, as shown in figure 42 . in this circuit, the second amplifier, a2, provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data, d, which is incremented from code zero (v out = ?v ref ) to midscale (v out = 0 v) to full scale (v out = +v ref ). ref n ref out v d vv ? ? ? ? ? ? ? = ? 1 2 where d is the fractional representation of the digital word loaded to the dac and n is the resolution of the dac. d= 0 to 255 (8-bit ad5426) = 0 to 1023 (10-bit ad5432) = 0 to 4095 (12-bit ad5443) when v in is an ac signal, the circuit performs 4-quadrant multiplication. table 6 shows the relationship between digital code and the expected output voltage for bipolar operation (ad5426, 8-bit device). table 6. bipolar code table digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 ?v ref (127/128) 0000 0000 ?v ref (128/128) stability in the i-to-v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible and proper pcb layout techniques must be employed. since every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response that can cause ringing or instability in closed-loop applications. an optional compensation capacitor, c1, can be added in parallel with r fb for stability, as shown in figure 41 and figure 42 . too small a value of c1 can produce ringing at the output, while too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for compensation. v out =?v ref to +v ref sclk sdin gnd v ref 10v sync i out 2 i out 1 r fb agnd ad5426/ ad5432/ ad5443 r1 r2 a1 v ref v dd v dd c1 notes 1. r1 and r2 are used only if gain adjustment is required. adjust r1 for v out = 0v with code 10000000 loaded to dac. 2. matching and tracking is essential for resistor pairs r3 and r4. 3. c1 phase compensation (1pf to 2pf) may be required if a1/a2 is a high speed amplifier. microcontroller r4 10k r5 20k r3 20k a2 a1 03162-043 figure 42. bipolar operation
ad5426/ad5432/ad5443 rev. c | page 17 of 28 single-supply applications current mode operation these dacs are specified and tested to guarantee operation in single-supply applications. in the current mode circuit of figure 43 , i out 2 and hence i out 1 is biased positive by an amount applied to v bias . v out gnd v in i out 2 i out 1 r fb a1 v ref v dd v bias v dd c1 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. a1 03162-044 a2 figure 43. single-supply current mode operation in this configuration, the output voltage is given by v out = { d ( r fb / r dac ) ( v bias ? v in )} + v bias as d varies from 0 to 255 (ad5426), 1023 (ad5432) or 4095 (ad5443), the output voltage varies from v out = v bias to v out = 2 v bias ? v in v bias should be a low impedance source capable of sinking and sourcing all possible variations in current at the i out 2 terminal without any problems. it is important to note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source drain drive voltage. as a result, their on resistance differs, which degrades the linearity of the dac. see figure 15 to figure 20 . voltage switching mode of operation figure 44 shows these dacs operating in the voltage switching mode. the reference voltage, v in , is applied to the i out 1 pin, i out 2 is connected to agnd, and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single- supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance), thus an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance, but one that varies with code. therefore, the voltage input should be driven from a low impedance source. v in r2 r1 v out gnd i out 1 r fb a1 v ref v dd v dd notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. 03162-045 figure 44. single-supply voltage switching mode operation it is important to note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source drain drive voltage. as a result, their on resistance differs, which degrades the linearity of the dac. also, v in must not go negative by more than 0.3 v or an internal diode turns on, exceeding the maximum ratings of the device. in this type of application, the full range of multiplying capability of the dac is lost. positive output voltage note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistors tolerance errors. to generate a negative reference, the reference can be level shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v, respectively, as shown in figure 45 . notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v out = 0v to +2.5v gnd i out 2 i out 1 r fb a1 v ref v dd = 5v v dd c1 gnd v in v out adr03 ?2.5v ?5v +5v 03162-046 figure 45. positive voltage output with minimum of components
ad5426/ad5432/ad5443 rev. c | page 18 of 28 adding gain in applications where the output voltage is required to be greater than v in , gain can be added with an additional external amplifier or it can be achieved in a single stage. it is important to consider the effect of temperature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. instead, the circuit shown in figure 46 is a recommended method of increasing the gain of the circuit. r1, r2, and r3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required. r1 r3 r2 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. v out gnd i out 2 i out 1 r fb a1 v ref v dd v dd c1 03162-047 figure 46. increasing gain of current output dac dacs used as a divider or programmable gain element current-steering dacs are very flexible and lend themselves to many different applications. if this type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor as shown in figure 47 , then the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ?n the output voltage is v out = ?v in / d = ?v in /(1 ? 2 ?n ) as d is reduced, the output voltage increases. for small values of d, it is important to ensure that the amplifier does not saturate and also that the required accuracy is met. for example, an 8-bit dac driven with the binary code 0x10 (00010000), that is, 16 decimal, in the circuit of figure 47 should cause the output voltage to be 16 v in . however, if the dac has a linearity specification of 0.5 lsb, then d can in fact have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage will be in the range 15.5 v in to 16.5 v in an error of +3% even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. since only a fraction d of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage has to change as follows: output error voltage due to dac leakage = (leakage r )/ d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k, ? and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv. gnd i out 1 i out 2 r fb v ref v dd v dd additional pins omitted for clarity. v out v in 03162-048 figure 47. current steering dac as a divider or programmable gain element reference selection when selecting a reference for use with the ad5426 series of current output dacs, pay attention to the references output voltage temperature coefficient specification. this parameter not only affects the full-scale error, but can also affect the linearity (inl and dnl) performance. the reference temperature coefficient should be consistent with the system accuracy specifications. for example, an 8-bit system required to hold its overall specification to within 1 lsb over the temperature range 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12-bit system with the same temperature range to overall specification within 2 lsbs requires a maximum drift of 10 ppm/c. by choosing a precision reference with low output temperature coefficient this error source can be minimized. table 7 suggests some references available from analog devices that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. the input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the dac) of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the dac to be nonmonotonic. in general, the input offset voltage should be a fraction (~ <1/4) of an lsb to ensure monotonic behavior when stepping through codes.
ad5426/ad5432/ad5443 rev. c | page 19 of 28 the input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent any significant errors in 12-bit applications. common-mode rejection of the op amp is important in voltage switching circuits since it produces a code-dependent error at the voltage output of the circuit. most op amps have adequate common-mode rejection at an 8-, 10-, or 12-bit resolution. provided the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, it is important to minimize capacitance at the v ref of the dac. this is done by using low input capacitance buffer amplifiers and careful board design. most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals,. there is a large range of single-supply amplifiers available from analog devices. table 7. suitable adi precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise v p-p package adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 tsot-23, sc70 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot-23, sc70 adr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot-23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic-8 adr435 5 0.04 3 0.8 8 soic-8 adr391 2.5 0.16 9 0.12 5 tsot-23 adr395 5 0.10 9 0.12 8 tsot-23 table 8. suitable adi precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 0.4 500 msop, soic-8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic-8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic-8 table 9. suitable adi high speed op amps part no. supply voltage (v) bw @ a cl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1,500 6,000 soic-8, sot-23, msop ad8021 2.5 to 12 490 100 1,000 10,500 soic-8, msop ad8038 3 to 12 350 425 3,000 750 soic-8, sc70-5 ad9631 2 to 6 320 1,300 10,000 7,000 soic-8
ad5426/ad5432/ad5443 rev. c | page 20 of 28 serial interface the ad5426/ad5432/ad5443 have an easy to use 3-wire inter- face that is compatible with spi/qspi/microwire and dsp interface standards. data is written to the device in 16 bit words. this 16-bit word consists of 4 control bits and either 8 , 10 , or 12 data bits as shown in figure 48 , figure 49 , and figure 50 . the ad5443 uses all 12 bits of dac data. the ad5432 uses 10 bits and ignores the 2 lsbs, while the ad5426 uses 8 bits and ignores the last 4 bits. low power serial interface to minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . the sync of the ad5426/ad5432/ad5443 needs to be synchronous with the microprocessor control. unfinished data frames are latched into the part and will affect the output. dac control bits c3 to c0 control bits c3 to c0 allow control of various functions of the dac, as seen in table 10 . default settings of the dac on power-on are as follows: data is clocked into the shift register on falling clock edges and daisy-chain mode is enabled. device powers on with zero-scale load to the dac register and i out lines. the dac control bits allow the user to adjust certain features on power-on, for example, daisy-chaining may be disabled if not in use, active clock edge may be changed to rising edge, and dac output may be cleared to either zero scale or midscale. the user may also initiate a readback of the dac register contents for verification purposes. table 10. dac control bits c3 c2 c1 c0 function implemented 0 0 0 0 no operation (power-on default) 0 0 0 1 load and update 0 0 1 0 initiate readback 0 0 1 1 reserved 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 reserved 1 0 0 1 daisy-chain disable 1 0 1 0 clock data to shift register on rising edge 1 0 1 1 clear dac output to zero scale 1 1 0 0 clear dac output to midscale 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved db0 (lsb) db15 (msb) c3 c2 c1 c0 xx db7 db6 db5 db4 db3 db2 db0db1 xx data bits control bits 03162-049 figure 48. ad5426 8-bit input shift register contents db5 db4 db3 db2 db0db1 db0 (lsb) db15 (msb) c3 c2 c1 c0 db7 db6 db8db9 xx data bits control bits 03162-050 figure 49. ad5432 10-bit inpu t shift register contents db7 db6 db5 db4 db3 db2 db0 db0 (lsb) db15 (msb) db1 c3 c2 c1 c0 db11 db10 db8 db9 data bits control bits 03162-051 figure 50. ad5443 12-bit inpu t shift register contents sync function sync is an edge-triggered input that acts as a frame synchro- nization signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, sync should be taken low observing the minimum sync falling to sclk falling edge setup time, t 4 . daisy-chain mode daisy-chain is the default power-on mode. to disable the daisy chain function, write 1001 to the control word. in daisy-chain mode, the internal gating on sclk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk (this is the default, use the control word to change the active edge) and is valid for the next device on the falling edge (default). by connecting this line to the d in input on the next device in the chain, a multidevice interface is constructed. sixteen clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 16 n where n is the total number of devices in the chain. see the timing diagram in . figure 4 when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data being clocked into the input shift register. a burst clock containing the exact number of clock cycles may be used and sync taken high some time later. after the rising edge of sync , data is automatically transferred from each devices input shift register to the addressed dac. when control bits = 0000, the device is in no operation mode. this may be useful in daisy-chain applications where the user does not want to change the settings of a particular dac in the chain. simply write 0000 to the control bits for that dac and the following data bits will be ignored. to re-enable the daisy- chain mode, if disabled, a power recycle is required.
ad5426/ad5432/ad5443 rev. c | page 21 of 28 standalone mode after power-on, write 1001 to the control word to disable daisy- chain mode. the first falling edge of sync resets a counter that counts the number of serial clocks, ensuring the correct number of bits are shifted in and out of the serial shift registers. a rising edge on sync during a write causes the write cycle to be aborted. after the falling edge of the 16th sclk pulse, data is auto- matically transferred from the input shift register to the dac. for another serial transfer to take place, the counter must be reset by the falling edge of sync . microprocessor interface microprocessor interfacing to this family of dacs is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the devices require a 16-bit word with a data valid default on the falling edge of sclk, but this is changeable via the control bits in the data-word. adsp-21xx to ad5426/ad5432/ad5443 interface the adsp-21xx family of dsps are easily interfaced to this family of dacs without extra glue logic. figure 51 shows an example of an spi interface between the dac and the adsp-2191m. sck of the dsp drives the serial data line, din. sync is driven from one of the port lines, in this case spixsel . sclk sck ad5426/ ad5432/ ad5443 spixsel sdin mosi adsp-2191 03162-052 additional pins omitted for clarity. sync figure 51. adsp-2191 spi-to-ad5426/ad5432/ad5443 interface a serial interface between the dac and dsp channel synchronous serial port (sport) is shown in figure 52 . in this interface example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsps serial clock and clocked into the dac input shift register on the falling edge of its sclk. the update of the dac output takes place on the rising edge of the sync signal. communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup and hold, data delay and data setup and hold, and sclk width. the dac interface expects a t4 ( sync falling edge to sclk falling edge setup time) of 13 ns minimum. consult the adsp-21xx user manual for information on clock and frame sync frequencies for the sport register. shows the sport control register. table 11 03162-053 sclk sclk sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191 additional pins omitted for clarity. ad5426/ ad5432/ ad5443 figure 52. adsp-2101/adsp-2103/adsp-2191 sport to ad5426/ad5432/ad5443 interface table 11. sport control register setup name setting description tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right-justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16-bit data-word adsp-bf5x to ad5426/ad5432/ad5443 interface the adsp-bf5xx family of processors has an spi-compatible port that enables the processor to communicate with spi- compatible devices. a serial interface between the adsp-bf5xx and the ad526/ad5432/ad5443 dac is shown in figure 53 . in this configuration, data is transferred through the master output/slave input (mosi) pin. sync is driven by the spi chip select pin, which is a reconfigured programmable flag pin. 03162-054 sclk sck ad5444 sync spixsel sdin mosi adsp-bf5xx additional pins omitted for clarity. figure 53. adsp-bf5xx-to-ad5426/ad5432/ad5443 interface the adsp-bf5xx processor incorporates the sport. a serial interface between the dac and the dsp sport is shown in figure 54 . when the sport is enabled, initiate transmission by writing a word to the tx register. the data is clocked out on each rising edge of the dsps serial clock and clocked into the dacs input shift register on the falling edge of its sclk. the dac output is updated by using the transmit frame synchro- nization (tfs) line to provide a sync signal. 03162-055 sclk sclk ad5444 sync tfs sdin dt adsp-bf5xx additional pins omitted for clarity. figure 54. adsp-bf5xx-to-ad5426/ad5432/ad5443 interface
ad5426/ad5432/ad5443 rev. c | page 22 of 28 80c51/80l51 to ad5426/ad5432/ad5443 interface 03162-057 mosi sclk pc7 sdin sck mc68hc11 additional pins omitted for clarity. sync ad5426/ ad5432/ ad5443 a serial interface between the dac and the 8051 is shown in figure 55 . txd of the 8051 drives sclk of the dac serial interface, while rxd drives the serial data line, d in . p3.3 is a bit- programmable pin on the serial port and is used to drive sync . when data is to be transmitted to the switch, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. to load data correctly to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between the dac and microcontroller interface. p3.3 is taken high following the completion of this cycle. the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the dac input register requires its data with the msb as the first bit received. the transmit routine should take this into account. figure 56. 68hc11/68l11-to-ad5426/ad5432/ad5443 interface microwire to ad5426/ ad5432/ad5443 interface figure 57 shows an interface between the dac and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the dac input shift register on the rising edge of sk, which corresponds to the falling edge of the dacs sclk. 03162-058 cs sclk sk sdin so microwire additional pins omitted for clarity. sync ad5426/ ad5432/ ad5443 03162-056 sync p1.1 sclk txd sdin rxd 8051 additional pins omitted for clarity. ad5426/ ad5432/ ad5443 figure 57. microwire-to-ad5426/ad5432/ad5443 interface pic16c6x/7x to ad5426/ad5432/ad5443 the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user manual. in this example, i/o port ra1 is being used to provide a sync signal and to enable the serial port of the dac. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. shows the connection diagram. figure 58 figure 55. 80c51/80l51-to-ad5426/ad5432/ad5443 interface mc68hc11 interface to ad5426/ad5432/ad5443 interface figure 56 shows an example of a serial interface between the dac and the mc68hc11 microcontroller. the spi on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)see the 68hc11 user manual. sck of the 68hc11 drives the sclk of the dac interface, the mosi output drives the serial data line (din) of the ad5426/ad5432/ad5443. the sync signal is derived from a port line (pc7). when data is being transmitted to the dac, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, pc7 is left low after the first eight bits are transferred and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. 03162-059 ra1 sclk sck/rc3 sdin sdi/rc4 pic16c6x/7x additional pins omitted for clarity. sync ad5426/ ad5432/ ad5443 figure 58. pic16c6x/7x-to-ad5426/ad5432/ad5443 interface if the user wants to verify the data previously written to the input shift register, the sdo line can be connected to miso of the mc68hc11, and with sync low, the shift register would clock data out on the rising edges of sclk.
ad5426/ad5432/ad5443 rev. c | page 23 of 28 pcb layout and power supply decoupling in any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5426/ad5432/ad5443 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close to the device as possible. the dac should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. low esr, 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize on high frequency performance, the i-to-v amplifier should be located as close to the device as possible. evaluation board for the ad5426/ad5432/ad5443 series of dacs the evaluation board consists of a 12-bit ad5443 and a current-to-voltage amplifier, the ad8065. included on the evaluation board is a 10 v reference, the adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. operating the evaluation board power supplies the board requires 12 v and +5 v supplies. the +12 v v dd and v ss are used to power the output amplifier, while the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors. link1 (lk1) is provided to allow selection between the on-board reference (adr01) or an external reference applied through j2. for the ad5426/ad5432/ad5443 use link2 in the sdo position.
ad5426/ad5432/ad5443 rev. c | page 24 of 28 v dd p1?13 p1?5 p1?4 p1?2 p1?3 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 sclk sdin ldac sclk sclk sdin sync sdo gnd i out 2 v dd r fb v ref v dd1 v ref v dd +v in v out trim gnd i out 1 ad5426/ ad5432/ ad5443 u1 u3 c1 0.1 f p2?3 p2?2 p2?1 p2?4 agnd v ss v dd1 v dd c11 0.1 f c12 10 f c3 10 f c4 0.1 f c5 0.1 f c13 0.1 f c14 10 f c15 0.1 f c16 10 f + u2 adr01ar j2 c9 10 f c10 0.1 f r1 = 0 ad8065ar lk2 lk1 a b 7 6 5 4 1 3 9 10 8 sdin sync v ref tp1 sdo/ldac sdo/ldac sync c2 10 f + c5 4.7pf 3 6 2 7 4 2 v out j1 2 5 4 6 + c7 10 f c8 0.1 f v ss + j3 j4 j5 j6 + + 03162-060 v? v+ figure 59. schematic of ad5426/ad5432/ad5443 evaluation board 03161-048 eval?ad5426/ ad5432/ad5443eb p1 p2 j2 j6 j5 j4 u1 u3 c11 u2 j3 vref vref j1 vout lk1 sdo/ldac sdo/ldac c10 c13 c14 c9 c1 r1 c2 c3 c6 c4 c16 c15 sync sync sdin sdin sclk sclk ldac lk2 sdo vdd vss vdd1 agnd tp1 c8 figure 60. silkscreencomponent side view (top layer)
ad5426/ad5432/ad5443 rev. c | page 25 of 28 03161-047 figure 61. component side artwork
ad5426/ad5432/ad5443 rev. c | page 26 of 28 03161-049 figure 62. solder side artwork
ad5426/ad5432/ad5443 rev. c | page 27 of 28 overview of ad54xx and ad55xx devices table 12. part no. resolution no. dacs inl (lsb) interface package features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial rj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 50 mhz serial interface ad5415 12 2 1 serial ru-24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp-40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial rj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width
ad5426/ad5432/ad5443 rev. c | page 28 of 28 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 63. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model resolution (bit) inl (lsb) temperature rang e package description package option branding ad5426yrm 8 0.25 ?40c to +125c 10-lead msop rm-10 d1q ad5426yrm-reel 8 0.25 ?40c to +125c 10-lead msop rm-10 d1q ad5426yrm-reel7 8 0.25 ?40c to +125c 10-lead msop rm-10 d1q ad5426yrmz 1 8 0.25 ?40c to +125c 10-lead msop rm-10 d6w ad5426yrmz-reel 1 8 0.25 ?40c to +125c 10-lead msop rm-10 d6w ad5426yrmz-reel7 1 8 0.25 ?40c to +125c 10-lead msop rm-10 d6w ad5432yrm 10 0.5 ?40c to +125c 10-lead msop rm-10 d1r ad5432yrm-reel7 10 0.5 ?40c to +125c 10-lead msop rm-10 d1r ad5432yrmz 1 10 0.5 ?40c to +125c 10-lead msop rm-10 d1r# ad5432yrmz-reel 1 10 0.5 ?40c to +125c 10-lead msop rm-10 d1r# ad5432yrmz-reel7 1 10 0.5 ?40c to +125c 10-lead msop rm-10 d1r# ad5443yrm 12 1 ?40c to +125c 10-lead msop rm-10 d1s ad5443yrm-reel 12 1 ?40c to + 125c 10-lead msop rm-10 d1s ad5443yrm-reel7 12 1 ?40c to +125c 10-lead msop rm-10 d1s ad5443yrmz 1 12 1 ?40c to +125c 10-lead msop rm-10 d1s# ad5443yrmz-reel 1 12 1 ?40c to +125c 10-lead msop rm-10 d1s# AD5443YRMZ-REEL7 1 12 1 ?40c to +125c 10-lead msop rm-10 d1s# eval-ad5426eb evaluation board eval-ad5432eb evaluation board eval-ad5443eb evaluation board eval-ad5443-dbrdz 1 evaluation board 1 z = rohs compliant part, # denotes rohs co mpliant product may be top or bottom marked. ?2004C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03162-0-2/09(c)

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